EEPROMs (Electrically Erasable and Programmable Read Only Memories) are widely used as a nonvolatile semiconductor memory device that is electrically erasable and programmable. These memory devices, which are represented by a widely used flash memory, have a conductive floating gate surrounded by an oxide or a trap insulator under a MOS (Metal Oxide Semiconductor) transistor gate. They use an electrical charge in the floating gate or trap insulator as stored information and read it as a transistor threshold value. The trap insulator is an insulator that is capable of storing an electrical charge. A typical example of the trap insulator is a silicon nitride film. When an electrical charge is injected into/released from such an electrical charge storage region, the MOS transistor threshold value is shifted so that the functionality of a storage element is exercised. Split gate cell based on a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) film is known as a flash memory using a silicon nitride film.
Advantages derived from the use of a silicon nitride film as an electrical charge storage region for the above memory include 1) excellent data retention reliability is provided because an electrical charge stored discretely, and 2) the top and bottom oxides for the silicon nitride film can be thinned because excellent data retention reliability is provided so that the voltage for programming/erase can be lowered.
Advantages provided by the use of a split gate cell include 1) hot electron injection into the silicon nitride film can be achieved by a source side injection method so as to provide excellent electron injection efficiency and permit high-speed, low-current programming, and 2) the peripheral circuit scale can be rendered small because programming/erase control is exercised with ease.
Two known methods are used for erasing the above memory: tunneling erase method and hot hole injection method. The memory cell based on the tunneling erase method is described, for instance, in Patent Document 1 (Japanese Patent JP-A No. 102466/2001). The memory cell based on the BTBT hot hole injection erase method is described, for instance, in Patent Document 2 (U.S. Pat. No. 5,969,383), Patent Document 3 (U.S. Pat. No. 6,248,633), and Patent Document 4 (Japanese Patent JP-A No. 46002/2003).
When the tunneling erase method is used, by applying electric field to the silicon nitride film, electrons, which are injected into the silicon nitride film by programming, tunnel through the top or bottom oxide to a gate or a substrate.
When the BTBT hot hole injection method is used, on the other hand, the electrons are not extracted. Instead, the threshold value is changed by injecting positively charged holes. As described on pages 157 through 160 of IEEE International Electron Devices Meeting 2003, it is known that hole injection is accomplished by generating holes by means of BTBT (Band-To-Band Tunneling), performing electric field acceleration of the holes, and injecting the holes into an insulator (see Non-patent Document 1).    [Patent Document 1] Japanese Patent JP-A No. 102466/2001 (equivalent to U.S. Pat. No. 6,255,166)    [Patent Document 2] U.S. Pat. No. 5,969,383    [Patent Document 3] U.S. Pat. No. 6,248,633    [Patent Document 4] Japanese Patent JP-A No. 46002/2003    [Non-patent Document 1] IEEE International Electron Devices Meeting 2003, pp. 157-160
Here, we compare the tunneling erase method and hole injection method (BTBT hot hole injection method). When the tunneling erase method is employed, there is a tradeoff between the data retention characteristic and erase characteristic. To improve the data retention characteristic, it is necessary to increase the thicknesses of oxides on upper and lower side of the silicon nitride film for decreasing electrical charge leakage or the thickness of the silicon nitride film for increasing the number of traps. However, since it is hard to have an electrical charge tunnel through a thick oxide during an erase operation, a low erase speed is lowered. To raise the erase speed, it is necessary to increase the erase voltage. However, an increase in the erase voltage enlarges the scale of a peripheral circuit, thereby increasing the chip cost. The oxide for electron extraction is limited to a small film thickness permitting electron tunneling so that the data retention characteristic is restricted.
Further, since electrons injected for programming are extracted for erase purposes, the threshold value prevailing after erase cannot be lowered below an initial threshold voltage at which the silicon nitride film is electrically neutral. If the threshold value cannot be sufficiently decreased, a large read current cannot be obtained. As a result, it is difficult to provide an increased read speed.
If the hole injection erase method (BTBT hot hole injection erase method) is used, on the other hand, the threshold value prevailing after erase can be shifted from the initial level to the negative side. In other words, since positive charges are injected and stored in an insulator, the threshold value can be smaller than the initial value and negative. This ensures that a larger amount of current can flow. Therefore, the hole injection erase method is suitable for a high-speed operation of a semiconductor circuit. Under these circumstances, the hole injection erase method is highlighted in recent years.
When an erase operation is performed by the positive hole injection erase method (BTBT hot hole injection erase method), a positive voltage is applied to a source diffusion layer of an NMOS-based memory cell and a negative voltage is applied to a gate electrode. Holes generated at the end of the source diffusion layer by means of BTBT can be accelerated by an electric field that is generated by a high voltage applied to the source diffusion layer and gate electrode, and injected into the silicon nitride film for erase purposes.
However, the studies conducted by the inventor of the present invention have revealed that the use of the hole injection erase method (BTBT hot hole injection erase method) accumulates holes because hole injection is locally conducted. This hole accumulation deteriorates the erase characteristic and electrical charge retention characteristic.
When the hole injection erase method is used, the above-mentioned erase characteristic deterioration occurs as described below. When a negative potential is given to the memory gate (MG) while a positive potential is given to the source (MS), the hot holes for erase operation are generated at the end of the source region MS as shown in FIG. 30 and injected into the entire region of a nitride film (S/N), which faces a silicon substrate. As a result, the holes (holes) are accumulated in the nitride film (c in FIG. 30) that is positioned directly above the hole generation section (b in FIG. 30) during the erase operation. FIG. 29 shows a cross section of an essential part that indicates a location at which hot electrons are generated when a nonvolatile semiconductor memory device (flash memory) performs programming. This figure schematically shows how electrons are injected into the charge storage section at the time of programming. FIG. 30 shows a cross section of an essential part that indicates a location at which hot holes are generated when the nonvolatile semiconductor memory device performs an erase. This figure schematically shows how holes are injected into the charge storage section at the time of an erase. The flash memory components shown in FIGS. 29 and 30 are not described herein because they are assigned the same reference numerals as the counterparts that will be described later in conjunction with embodiments of the present invention.
When the holes accumulate, the vertical electric field on the insulator-substrate interface at the end of the source diffusion layer (MS) decreases to decrease the amount of hole generation, thereby bringing the erase operation to a stop. When programming is repeatedly performed, the number of holes stored in the nitride film above the hole generation section increases, and the hole generation process comes to a stop before the electrons injected by programming are completely erased. As a result, the repeated execution of a programming/erase operation is restricted.
Further, the accumulated holes deteriorate the charge retention characteristic. In other words, the electrical charge must be retained by injected electrons in a programming state. However, the BTBT-based hole injection operation generates holes at the end of the source diffusion layer as described earlier. Therefore, if the holes are excessively accumulated directly above the diffusion layer, the holes are locally accumulated even in a programming state. As a result, threshold value changes caused by recombination of holes and electrons are observed as retention characteristic deterioration.